1. Field Of The Invention
This invention relates to an analog to digital convertor apparatus and is suitably applied to a signal comparison unit of analog-digital converter which outputs analog input signals upon sequentially converting to digital signals, for example.
2. Description Of The Related Art
Heretofore, in the fields of audio apparatus and meter instruments, an analog-to-digital converter (hereinafter referred to as A/D converter) is used in order to signal process various analog signals digitally, such as audio signal for recording or reproducing, and various conversion systems have been proposed according to the field used and preciseness and speed required.
Especially, in the case where high speed operation and preciseness are required, it is common that a parallel (flash) type A/D converter or series-parallel (subranging) type A/D converter is used and various circuit constructions have been considered corresponding to the required speed and preciseness even in the same conversion system.
More specifically, even in the same parallel A/D converter as shown in FIGS. 1 and 2, various circuit constructions have been considered corresponding to the number of bits and preciseness.
In a case of parallel type A/D converter 1 having 8-bit resolution (FIG. 1), when 255 reference electric potentials are generated at each reference resistance R1-R256 by supplying reference voltages VRT and VRB to both terminals of 256 reference resistances R1-R256 which are connected in series, each reference electric potential generated and analog signal V.sub.IN to be inputted in common to each input terminal is compared respectively at comparators. C1-C255.
This parallel type A/D converter 1 supplies comparison outputs of comparators C1-C255 to an encoder 2 through differentiating circuits D1-D255 which are constituted by AND circuits, and outputs sequentially 8-bit 2 value data converted by said encoder 2 through a logical circuit which is constituted by a buffer B1 and OR circuits OR1-OR8 and an output buffer 3 as output data D0-D7.
However, since it is necessary to have 2.sup.10 -1 (=1023) comparators if we try to construct the parallel type A/D converter having 10-bit resolution in accordance with the construction as described above, a parallel type A/D converter 5 which can be constituted by 2.sup.9 -1 (=511) comparators by using interpolation has been proposed.
FIG. 2 is a block diagram showing a part of parallel A/D converter 5, and comparators Cm and Cm-1 which are constituted by differential amplifiers latch a comparison output S.sub.m, an inversion output IS.sub.m and a comparison output S.sub.m-1, an inversion output IS.sub.m-1 at latch circuits 6m and 6m-1 respectively, and simultaneously the number of comparators will be decreased by latching the comparison output S.sub.m and the inverse output IS.sub.m-1 of adjacent comparators Cm and Cm-1 at the latch circuit 7m for interpolation and supplying to a decoder 8.
At this point, reference electric potentials V.sub.REF1 and V.sub.REF2 are supplied to comparators Cm and Cm-1 respectively, and the comparison result of said reference electric potentials V.sub.REF1 and V.sub.REF2 (&gt;V.sub.REF1) and the analog signal V.sub.IN will be outputted as the comparison output S.sub.m, inversion output IS.sub.m and the comparison output S.sub.m-1, inversion output IS.sub.m-1 (FIGS. 3A and 3B).
As shown in FIGS. 2 and 3B, the latch circuits 6m and 6m-1 inverse the latch output when the analog input signal V.sub.IN exceeds reference voltage V.sub.REF1 and V.sub.REF2 and the comparison output Sm to be inputted from comparators Cm and Cm-1 of the previous stage and the inversion output IS.sub.m, and the comparison output S.sub.m-1 and the inverse output IS.sub.m-1 intersect respectively, and also the latch circuit 7m inverses the latch output when the comparison output S.sub.m of comparator Cm and the inversion output IS.sub.m-1 of comparator Cm-1 intersect each other.
On the other hand, since the latch circuit 7m inverses the latch output when an intermediate electric potential between reference voltages V.sub.REF1 and V.sub.REF2 (hereinafter referred to as virtual reference electric potential), which is not given in the parallel type A/D converter 5 practically, and the input analog signal V.sub.IN intersect each other and thus the number of comparators will be decreased by half.
With this arrangement, the parallel A/D converter 5 is able to decrease the number of comparators by half, and the input capacity which will be especially important in the case of high speed driving can be decreased and simultaneously, differential linearity error can be decreased in utilizing the virtual reference electric potential.
As shown in FIG. 4A in the conventional parallel A/D converter 1, the reference electric potential V.sub.REF (N) shifts and the code N to overlap with the reference electric potential V.sub.REF (N+1) disappears; on the other hand, in case of interpolating by using the virtual reference electric potential as shown in FIG. 4B, since reference electric potentials V.sub.REF (N-1) and V.sub.REF (N+1) are virtual reference electric potentials to be formed by interpolation, virtual reference electric potentials V.sub.REF (N-1) and V.sub.REF (N+1) shift corresponding to the shift of reference electric potential V.sub.REF (N) if the reference electric potential V.sub.REF (N) shifts.
However, there has been a problem that this A/D conversion method cannot interpolate more than that number of comparators in spite of the fact that this method can interpolate the number of comparators by half.
Similarly, as the A/D converter having 10-bit resolution, a 3 stage A/D converter, which is capable of decreasing the number of comparators further, having low manufacturing cost and decreasing electric power consumption, has been proposed.
As shown in FIG. 5, this A/D converter 10 generates upper 4-bit data at first by 16 reference potentials at the primary stage (FIG. 5A), at the following second stage, generates (0)-(7) medium 3-bit data and (-1) and (8) surplus bits (FIG. 5B), and at the last third stage, it obtains lower 3-bit (FIG. 5C), and it is composed of a total of 32 comparators.
At this point, the third stage of A/D converter 10 is constituted by connection of a pair of differential amplifiers 11A and 11B as shown in FIG. 6, and the input analog signal V.sub.IN is inputted to one input terminal and the second stage reference voltages V.sub.REF1 and V.sub.REF2 are inputted to the other input terminal respectively.
The differential amplifiers 11A and 11B are connected with two pairs of resistance sequences connected in series the resistance having a resistance ratio of 3:2:4:12 and by combining output voltages Va1-Va4 and Vb1-Vb4 which are differential voltages in connecting taps of each resistance, reference voltages divided into eight equal parts are generated by interpolation and conversion characteristic with minor connection errors can be obtained.
More specifically, as shown in FIG. 7, there are generated interpolation voltages V1, V2, V3, V4, V5, V6 and V7 which are obtained by dividing the second stage reference voltages V.sub.REF1 and V.sub.REF2 into eight equal parts, according to the voltage ratio of output voltages Vb1 and Va4 (=3:21), voltage ratio of output voltages Vb1 and Va3 (=3:9), the voltage ratio of output voltages Vb1 and Va2 (=3:5), the voltage ratio of output voltages Vb2 and Va2 (=5:5), the voltage ratio of output voltages Vb2 and Va1 (=5:3), the voltage ratio of output voltages Vb3 and Va1 (=9:3), and the voltage ratio of output voltages Vb4 and Va1 (=21:3).
However, in this case, more than a half of interpolation can be performed; on the other hand, it becomes necessary to have one additional differential amplifier. Difference in rate of delivery also arises because of difference in time constant for generating various differential outputs according to different resistance values. This could not be used for the parallel type A/D converter.